3/15/2024 0 Comments Verilog parse binary to decimalAdding three to any BCD digit greater than five does two things: first, at the next shift, the 3 that was added becomes 6, and that accounts for the difference in binary and BCD codes (BCD uses 10 binary codes, and binary uses 16) and second, adding 3 forces the MSB of the BCD digit to a 1, where it is “carried out” and into the next digit. Since BCD digits cannot exceed nine, a pre-shift number of five or more would result in a post-shift number of ten or more, which cannot be represented. This works because every left shift multiplies all BCD digits by two. After every shift, all BCD digits are examined, and 3 is added to any BCD digit that is currently 5 or greater. The binary number is left-shifted once for each of its bits, with bits shifted out of the MSB of the binary number and into the LSB of the accumulating BCD number. The “double dabble” algorithm is commonly used to convert a binary number to BCD. The Verilog code below illustrates converting a 4-digit BCD number to it’s binary equivalent. To find the binary equivalent, each BCD digit is multiplied by its weighted magnitude: 9 x 10^2 + 8 * 10^1 + 7 * 10^0, or 9 * 100 + 8 * 10+ 7 * 1. Consider the BCD number 987, stored as three 4-bit BCD codes: 1001 for 9 (digit 2), 1000 for 8 (digit 1), and 0111 for 7 (digit 0). Each BCD digit in a given number contributes a magnitude equal to the digit multiplied by its weight, and each digit’s weight is equal to 10 raised to the power of the digit’s position in the number. BCD numbers are representations of decimal (base 10) numbers, and like all modern number systems, BCD numbers use positional weighting. In order to compare results, all of the numbers were checked with an online IEEE 754 float converter. We can this program by breaking it into functions that allow us to run different values through it. The sign bit was set at the beginning of the program when we determined whether to flip the bits of the LHS register from 2’s complement. This tells us the number of shifts that need to be performed in order to reconstruct the floating-point number from IEEE format. The exponent value comes from the length that the most-significant 1-bit is in. This gives us a complete mantissa value for the result. If there are, we should round the last bit of the mantissa to 1. If the RHS value gets shifted too far to the right and we lose precision, we need to check if there are any 1-bits to the right of where the value gets cut off. Since we stored our fraction starting in the MSB, we take the value from that register, shift it to the right however many binary digits the left value takes up, and OR the mantissa LHS value with the RHS fraction. The RHS fractional value must be combined with the LHS value already stored in the result register. Then we apply the AND operation to the mask and the LHS value, and shift the result into the most significant bit for the mantissa value (position 22). To get the mantissa value, if there is a value in the left-hand argument, we find the most significant 1-bit and create a bit mask that is the length of the value excluding the most significant 1-bit. Knowing this value allows us to treat the integer value like a decimal so that we can use a doubling technique to find its binary fractional approximation. We do this by finding a power of 10 that is greater than the RHS argument. The RHS is passed in as an integer, so we need to convert it to a binary fraction. We convert the left-hand argument to a positive binary number even if it was stored as a negative (2’s compliment). The following approach was used to generate a floating point number: The following article discusses exactly what a floating point number is. A simple routine in Verilog HDL that converts integers into IEEE 754 Floating Point format.
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